URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] [mlite_pack.vhd] - Rev 264

Rev	Log message	Author	Age	Path
264	Latch address and byte_we in mem_ctrl.vhd	rhoads	6051d 13h	/mlite/trunk/vhdl/mlite_pack.vhd
202	Defined outputing PC as stage #0	rhoads	6290d 14h	/mlite/trunk/vhdl/mlite_pack.vhd
194	Implemented BREAK and SYSCALL opcodes	rhoads	6355d 10h	/mlite/trunk/vhdl/mlite_pack.vhd
139	Major changes -- updated to Plasma Version 3	rhoads	6701d 03h	/mlite/trunk/vhdl/mlite_pack.vhd
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7181d 01h	/mlite/trunk/vhdl/mlite_pack.vhd
128	Reset all registers, constants now upper case.	rhoads	7318d 12h	/mlite/trunk/vhdl/mlite_pack.vhd
125	Fixed pc_source_type comment.	rhoads	7337d 02h	/mlite/trunk/vhdl/mlite_pack.vhd
116	Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7518d 02h	/mlite/trunk/vhdl/mlite_pack.vhd
96	Simplify take_branch	rhoads	8041d 06h	/mlite/trunk/vhdl/mlite_pack.vhd
91	Removed unused alu_function_type entries	rhoads	8043d 00h	/mlite/trunk/vhdl/mlite_pack.vhd
70	pipeline	rhoads	8051d 01h	/mlite/trunk/vhdl/mlite_pack.vhd
62	updated LPM functions; mem_none->mem_fetch	rhoads	8059d 06h	/mlite/trunk/vhdl/mlite_pack.vhd
50	Update prototypes	rhoads	8070d 01h	/mlite/trunk/vhdl/mlite_pack.vhd
47	Altera	rhoads	8077d 02h	/mlite/trunk/vhdl/mlite_pack.vhd
44	Fixed signed 64-bit multiply	rhoads	8154d 15h	/mlite/trunk/vhdl/mlite_pack.vhd
43	Renamed M-lite to Plasma	rhoads	8157d 02h	/mlite/trunk/vhdl/mlite_pack.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8189d 08h	/mlite/trunk/vhdl/mlite_pack.vhd