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[/] [mlite/] [trunk/] [vhdl/] [mult.vhd] - Rev 350

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Rev Log message Author Age Path
350 root 5584d 22h /mlite/trunk/vhdl/mult.vhd
345 Commented out optional mult speedup rhoads 5656d 14h /mlite/trunk/vhdl/mult.vhd
196 Explained how to remove mult.vhd and use SW multiplication and division. rhoads 6322d 14h /mlite/trunk/vhdl/mult.vhd
139 Major changes -- updated to Plasma Version 3 rhoads 6685d 10h /mlite/trunk/vhdl/mult.vhd
132 Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly. rhoads 7165d 09h /mlite/trunk/vhdl/mult.vhd
128 Reset all registers, constants now upper case. rhoads 7302d 20h /mlite/trunk/vhdl/mult.vhd
121 Added Matthias Gruenewald's tri-state area-optimized option rhoads 7463d 23h /mlite/trunk/vhdl/mult.vhd
117 Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA. rhoads 7502d 10h /mlite/trunk/vhdl/mult.vhd
99 correct upper 32-bits for mult(-1,-1) rhoads 7922d 08h /mlite/trunk/vhdl/mult.vhd
97 added documentation rhoads 7991d 12h /mlite/trunk/vhdl/mult.vhd
90 Now multiplies two bits at a time rhoads 8027d 07h /mlite/trunk/vhdl/mult.vhd
47 Altera rhoads 8061d 10h /mlite/trunk/vhdl/mult.vhd
45 Fixed signed 64-bit multiply rhoads 8138d 23h /mlite/trunk/vhdl/mult.vhd
43 Renamed M-lite to Plasma rhoads 8141d 10h /mlite/trunk/vhdl/mult.vhd
39 Changed name to M-lite to avoid trademark issues. rhoads 8173d 15h /mlite/trunk/vhdl/mult.vhd
23 Fixed div -x/y. rhoads 8198d 09h /mlite/trunk/vhdl/mult.vhd
18 Fixed "divu $3,$4". "Div $3,$4" still has bug if $3*$4<0. rhoads 8200d 09h /mlite/trunk/vhdl/mult.vhd
7 Made writes 4 cycles, improved mem_ctrl.vhd rhoads 8215d 17h /mlite/trunk/vhdl/mult.vhd
2 MIPS-lite CPU core rhoads 8438d 15h /mlite/trunk/vhdl/mult.vhd

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