URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk/] [vhdl/] [reg_bank.vhd] - Rev 123

Rev	Log message	Author	Age	Path
123	Uncomment out the Altera portion. Xilinx users may need to re-comment out this section.	rhoads	7467d 21h	/mlite/trunk/vhdl/reg_bank.vhd
115	Matthias Grunewald's changes for Xilinx FPGA dual-port RAM.	rhoads	7581d 21h	/mlite/trunk/vhdl/reg_bank.vhd
108	changed interrupt vector from 0x30 to 0x3c	rhoads	7855d 18h	/mlite/trunk/vhdl/reg_bank.vhd
88	Cleanup spaces	rhoads	8106d 18h	/mlite/trunk/vhdl/reg_bank.vhd
74	pause in	rhoads	8114d 20h	/mlite/trunk/vhdl/reg_bank.vhd
55	Altera	rhoads	8123d 01h	/mlite/trunk/vhdl/reg_bank.vhd
48	Altera	rhoads	8133d 20h	/mlite/trunk/vhdl/reg_bank.vhd
47	Altera	rhoads	8140d 21h	/mlite/trunk/vhdl/reg_bank.vhd
43	Renamed M-lite to Plasma	rhoads	8220d 21h	/mlite/trunk/vhdl/reg_bank.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8253d 02h	/mlite/trunk/vhdl/reg_bank.vhd
24	Disable interrupts upon reset.	rhoads	8277d 20h	/mlite/trunk/vhdl/reg_bank.vhd
12	Better support for dual-port memories, removed old method	rhoads	8283d 20h	/mlite/trunk/vhdl/reg_bank.vhd
9	Support for generic_tpram dual-port RAM	rhoads	8288d 23h	/mlite/trunk/vhdl/reg_bank.vhd
8	Preparing to use dual-port memory for registers.	rhoads	8289d 21h	/mlite/trunk/vhdl/reg_bank.vhd
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8299d 02h	/mlite/trunk/vhdl/reg_bank.vhd
2	MIPS-lite CPU core	rhoads	8518d 02h	/mlite/trunk/vhdl/reg_bank.vhd