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[/] [mlite/] [trunk/] [vhdl/] [reg_bank.vhd] - Rev 132

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Rev	Log message	Author	Age	Path
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7182d 05h	/mlite/trunk/vhdl/reg_bank.vhd
128	Reset all registers, constants now upper case.	rhoads	7319d 16h	/mlite/trunk/vhdl/reg_bank.vhd
123	Uncomment out the Altera portion. Xilinx users may need to re-comment out this section.	rhoads	7405d 06h	/mlite/trunk/vhdl/reg_bank.vhd
115	Matthias Grunewald's changes for Xilinx FPGA dual-port RAM.	rhoads	7519d 06h	/mlite/trunk/vhdl/reg_bank.vhd
108	changed interrupt vector from 0x30 to 0x3c	rhoads	7793d 03h	/mlite/trunk/vhdl/reg_bank.vhd
88	Cleanup spaces	rhoads	8044d 03h	/mlite/trunk/vhdl/reg_bank.vhd
74	pause in	rhoads	8052d 05h	/mlite/trunk/vhdl/reg_bank.vhd
55	Altera	rhoads	8060d 10h	/mlite/trunk/vhdl/reg_bank.vhd
48	Altera	rhoads	8071d 05h	/mlite/trunk/vhdl/reg_bank.vhd
47	Altera	rhoads	8078d 06h	/mlite/trunk/vhdl/reg_bank.vhd
43	Renamed M-lite to Plasma	rhoads	8158d 06h	/mlite/trunk/vhdl/reg_bank.vhd
39	Changed name to M-lite to avoid trademark issues.	rhoads	8190d 11h	/mlite/trunk/vhdl/reg_bank.vhd
24	Disable interrupts upon reset.	rhoads	8215d 04h	/mlite/trunk/vhdl/reg_bank.vhd
12	Better support for dual-port memories, removed old method	rhoads	8221d 05h	/mlite/trunk/vhdl/reg_bank.vhd
9	Support for generic_tpram dual-port RAM	rhoads	8226d 08h	/mlite/trunk/vhdl/reg_bank.vhd
8	Preparing to use dual-port memory for registers.	rhoads	8227d 05h	/mlite/trunk/vhdl/reg_bank.vhd
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8236d 10h	/mlite/trunk/vhdl/reg_bank.vhd
2	MIPS-lite CPU core	rhoads	8455d 11h	/mlite/trunk/vhdl/reg_bank.vhd

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