URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk] - Rev 17

Rev	Log message	Author	Age	Path
17	Fixed "blez $0,target". Made LWL=LW and SWL=SW. Changed tabs to spaces.	rhoads	8222d 16h	/mlite/trunk
16	Fixed binary to HEX when the number of digits isn't a multiple of 4.	rhoads	8222d 16h	/mlite/trunk
15	Test all MIPS I opcodes.	rhoads	8222d 16h	/mlite/trunk
14	Fixed big-endian mode bugs	rhoads	8226d 16h	/mlite/trunk
13	Removed reg_bank configuration control	rhoads	8226d 16h	/mlite/trunk
12	Better support for dual-port memories, removed old method	rhoads	8226d 16h	/mlite/trunk
11	Added comment for DEBUG mode	rhoads	8226d 16h	/mlite/trunk
10	Add pause_in to process dependency, fixes "lw $4,0($4)"	rhoads	8226d 16h	/mlite/trunk
9	Support for generic_tpram dual-port RAM	rhoads	8231d 19h	/mlite/trunk
8	Preparing to use dual-port memory for registers.	rhoads	8232d 17h	/mlite/trunk
7	Made writes 4 cycles, improved mem_ctrl.vhd	rhoads	8238d 00h	/mlite/trunk
6	JAL now correctly sets r31 to instruction AFTER branch delay slot. Fixed interrupts.	rhoads	8241d 22h	/mlite/trunk
4	Update web page	rhoads	8460d 21h	/mlite/trunk
2	MIPS-lite CPU core	rhoads	8460d 22h	/mlite/trunk
1	Standard project directories initialized by cvs2svn.		8460d 22h	/mlite/trunk