URL https://opencores.org/ocsvn/mlite/mlite/trunk

Subversion Repositories mlite

[/] [mlite/] [trunk] - Rev 26

Rev	Log message	Author	Age	Path
26	Changed to gcc compiler. Strip off first 0x1000 bytes.	rhoads	8250d 06h	/mlite/trunk
25	opcodes target	rhoads	8250d 06h	/mlite/trunk
24	Disable interrupts upon reset.	rhoads	8250d 06h	/mlite/trunk
23	Fixed div -x/y.	rhoads	8250d 06h	/mlite/trunk
22	Switched to gcc compiler.	rhoads	8250d 06h	/mlite/trunk
21	Moved startup to boot.asm	rhoads	8250d 06h	/mlite/trunk
20	Startup code.	rhoads	8250d 06h	/mlite/trunk
19	Changed simili run to 40us.	rhoads	8252d 06h	/mlite/trunk
18	Fixed "divu $3,$4". "Div $3,$4" still has bug if $3*$4<0.	rhoads	8252d 06h	/mlite/trunk
17	Fixed "blez $0,target". Made LWL=LW and SWL=SW. Changed tabs to spaces.	rhoads	8252d 06h	/mlite/trunk
16	Fixed binary to HEX when the number of digits isn't a multiple of 4.	rhoads	8252d 06h	/mlite/trunk
15	Test all MIPS I opcodes.	rhoads	8252d 06h	/mlite/trunk
14	Fixed big-endian mode bugs	rhoads	8256d 06h	/mlite/trunk
13	Removed reg_bank configuration control	rhoads	8256d 06h	/mlite/trunk
12	Better support for dual-port memories, removed old method	rhoads	8256d 06h	/mlite/trunk
11	Added comment for DEBUG mode	rhoads	8256d 06h	/mlite/trunk
10	Add pause_in to process dependency, fixes "lw $4,0($4)"	rhoads	8256d 06h	/mlite/trunk
9	Support for generic_tpram dual-port RAM	rhoads	8261d 09h	/mlite/trunk
8	Preparing to use dual-port memory for registers.	rhoads	8262d 07h	/mlite/trunk
7	Made writes 4 cycles, improved mem_ctrl.vhd	rhoads	8267d 13h	/mlite/trunk