URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.0/] [rtl/] [vhdl/] [core/] [adder_block.vhd] - Rev 100

Rev	Log message	Author	Age	Path
100	added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. previous tag was incorrect, now updated	JonasDC	3970d 17h	/mod_sim_exp/tags/Release_1.0/rtl/vhdl/core/adder_block.vhd
12	updated comments, file is now completely according to design rules	JonasDC	4254d 05h	/mod_sim_exp/tags/Release_1.0/rtl/vhdl/core/adder_block.vhd
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4254d 10h	/mod_sim_exp/tags/Release_1.0/rtl/vhdl/core/adder_block.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4255d 05h	/mod_sim_exp/tags/Release_1.0/rtl/vhdl/core/adder_block.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4259d 11h	/mod_sim_exp/tags/Release_1.0/rtl/vhdl/core/adder_block.vhd