URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.0/] [rtl/] [vhdl/] [core/] [x_shift_reg.vhd] - Rev 100

Rev	Log message	Author	Age	Path
100	added version 1.0 tag for completeness. This version is the first version that is adapted to the opencores design rules. Also the code is cleaned up. previous tag was incorrect, now updated	JonasDC	3963d 05h	/mod_sim_exp/tags/Release_1.0/rtl/vhdl/core/x_shift_reg.vhd
21	changed x_i signal to xi	JonasDC	4240d 04h	/mod_sim_exp/tags/Release_1.0/rtl/vhdl/core/x_shift_reg.vhd
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4240d 04h	/mod_sim_exp/tags/Release_1.0/rtl/vhdl/core/x_shift_reg.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4247d 17h	/mod_sim_exp/tags/Release_1.0/rtl/vhdl/core/x_shift_reg.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4251d 23h	/mod_sim_exp/tags/Release_1.0/rtl/vhdl/core/x_shift_reg.vhd