URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [interface/] [plb/] [mont_mult1536.vhd] - Rev 80

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4137d 15h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mont_mult1536.vhd
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4177d 16h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mont_mult1536.vhd
43	made the core parameters generics	JonasDC	4249d 14h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mont_mult1536.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4289d 22h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mont_mult1536.vhd