URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.1/] [rtl/] [vhdl/] [interface/] [plb/] [mont_mult1536.vhd] - Rev 100

Rev	Log message	Author	Age	Path
80	renamed to version 1.1 to follow the versioning system	JonasDC	4120d 02h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mont_mult1536.vhd
49	First full stable version with documentation. Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.	JonasDC	4160d 02h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mont_mult1536.vhd
43	made the core parameters generics	JonasDC	4232d 01h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mont_mult1536.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4272d 08h	/mod_sim_exp/tags/Release_1.1/rtl/vhdl/interface/plb/mont_mult1536.vhd