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[/] [mod_sim_exp/] [tags/] [Release_1.1/] [sim/] [src/] [sim_input.txt] - Rev 49

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49 First full stable version with documentation.
Includes flexible pipeline design, PLB interface and the RAM and FIFO is still using xilinx primitives.
JonasDC 4155d 23h /mod_sim_exp/tags/Release_1.1/sim/src/sim_input.txt
35 new test values, 1st exponentiation gives error on result with new pipeline
commit for test purposes
JonasDC 4247d 21h /mod_sim_exp/tags/Release_1.1/sim/src/sim_input.txt
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation
JonasDC 4263d 22h /mod_sim_exp/tags/Release_1.1/sim/src/sim_input.txt

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