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[/] [mod_sim_exp/] [tags/] [Release_1.1] - Rev 27

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Rev	Log message	Author	Age	Path
27	test input values for multiplier_tb	JonasDC	4232d 15h	/mod_sim_exp/tags/Release_1.1
26	testbench for only the montgommery multiplier	JonasDC	4232d 15h	/mod_sim_exp/tags/Release_1.1
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4232d 15h	/mod_sim_exp/tags/Release_1.1
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4236d 00h	/mod_sim_exp/tags/Release_1.1
23	added descriptive comments	JonasDC	4236d 02h	/mod_sim_exp/tags/Release_1.1
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4238d 19h	/mod_sim_exp/tags/Release_1.1
21	changed x_i signal to xi	JonasDC	4240d 03h	/mod_sim_exp/tags/Release_1.1
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4240d 03h	/mod_sim_exp/tags/Release_1.1
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4244d 22h	/mod_sim_exp/tags/Release_1.1
18	updated stages with comments and renamed some signals for consistency	JonasDC	4245d 22h	/mod_sim_exp/tags/Release_1.1
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4246d 03h	/mod_sim_exp/tags/Release_1.1
16	package with modified generic parameter for register_n	JonasDC	4246d 16h	/mod_sim_exp/tags/Release_1.1
15	changed generic for register width from n to width for consistency	JonasDC	4246d 16h	/mod_sim_exp/tags/Release_1.1
14	changed comments, file is now according to OC design rules	JonasDC	4246d 16h	/mod_sim_exp/tags/Release_1.1
13	added some descriptive comments and added check for incorrect value's of width and block_width. File is now according to OC design rules	JonasDC	4246d 16h	/mod_sim_exp/tags/Release_1.1
12	updated comments, file is now completely according to design rules	JonasDC	4246d 16h	/mod_sim_exp/tags/Release_1.1
11	simulation output folder	JonasDC	4246d 19h	/mod_sim_exp/tags/Release_1.1
10	changed signal input port names to correct name	JonasDC	4246d 21h	/mod_sim_exp/tags/Release_1.1
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4246d 21h	/mod_sim_exp/tags/Release_1.1
8	added descriptive comments	JonasDC	4247d 00h	/mod_sim_exp/tags/Release_1.1

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[/] [mod_sim_exp/] [tags/] [Release_1.1] - Rev 27

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