URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [tags/] [Release_1.3/] [rtl] - Rev 8

Rev	Log message	Author	Age	Path
8	added descriptive comments	JonasDC	4281d 12h	/mod_sim_exp/tags/Release_1.3/rtl
7	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4281d 12h	/mod_sim_exp/tags/Release_1.3/rtl
6	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4281d 12h	/mod_sim_exp/tags/Release_1.3/rtl
4	Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation added descriptive comments	JonasDC	4281d 14h	/mod_sim_exp/tags/Release_1.3/rtl
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4282d 04h	/mod_sim_exp/tags/Release_1.3/rtl
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4286d 10h	/mod_sim_exp/tags/Release_1.3/rtl