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[/] [mod_sim_exp/] [tags/] [Release_1.4] - Rev 31

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31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4260d 07h /mod_sim_exp/tags/Release_1.4
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4260d 07h /mod_sim_exp/tags/Release_1.4
29 added software for generation of test input for the tesbenches JonasDC 4260d 20h /mod_sim_exp/tags/Release_1.4
28 updated makefile for new pipeline sources JonasDC 4260d 21h /mod_sim_exp/tags/Release_1.4
27 test input values for multiplier_tb JonasDC 4260d 21h /mod_sim_exp/tags/Release_1.4
26 testbench for only the montgommery multiplier JonasDC 4260d 21h /mod_sim_exp/tags/Release_1.4
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline
JonasDC 4260d 21h /mod_sim_exp/tags/Release_1.4
24 changed names of top-level module to mod_sim_exp_core JonasDC 4264d 06h /mod_sim_exp/tags/Release_1.4
23 added descriptive comments JonasDC 4264d 07h /mod_sim_exp/tags/Release_1.4
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4267d 01h /mod_sim_exp/tags/Release_1.4
21 changed x_i signal to xi JonasDC 4268d 08h /mod_sim_exp/tags/Release_1.4
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules
JonasDC 4268d 09h /mod_sim_exp/tags/Release_1.4
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic
JonasDC 4273d 04h /mod_sim_exp/tags/Release_1.4
18 updated stages with comments and renamed some signals for consistency JonasDC 4274d 03h /mod_sim_exp/tags/Release_1.4
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4274d 08h /mod_sim_exp/tags/Release_1.4
16 package with modified generic parameter for register_n JonasDC 4274d 21h /mod_sim_exp/tags/Release_1.4
15 changed generic for register width from n to width for consistency JonasDC 4274d 21h /mod_sim_exp/tags/Release_1.4
14 changed comments, file is now according to OC design rules JonasDC 4274d 22h /mod_sim_exp/tags/Release_1.4
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules
JonasDC 4274d 22h /mod_sim_exp/tags/Release_1.4
12 updated comments, file is now completely according to design rules JonasDC 4274d 22h /mod_sim_exp/tags/Release_1.4

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