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[/] [mod_sim_exp/] [tags/] [Release_1.4] - Rev 35

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Rev	Log message	Author	Age	Path
35	new test values, 1st exponentiation gives error on result with new pipeline commit for test purposes	JonasDC	4259d 20h	/mod_sim_exp/tags/Release_1.4
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4259d 21h	/mod_sim_exp/tags/Release_1.4
33	default pipeline changed to old version, there seems to be an occasional error with new version.	JonasDC	4259d 23h	/mod_sim_exp/tags/Release_1.4
32	new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default.	JonasDC	4260d 00h	/mod_sim_exp/tags/Release_1.4
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4260d 06h	/mod_sim_exp/tags/Release_1.4
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4260d 06h	/mod_sim_exp/tags/Release_1.4
29	added software for generation of test input for the tesbenches	JonasDC	4260d 19h	/mod_sim_exp/tags/Release_1.4
28	updated makefile for new pipeline sources	JonasDC	4260d 20h	/mod_sim_exp/tags/Release_1.4
27	test input values for multiplier_tb	JonasDC	4260d 20h	/mod_sim_exp/tags/Release_1.4
26	testbench for only the montgommery multiplier	JonasDC	4260d 20h	/mod_sim_exp/tags/Release_1.4
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4260d 20h	/mod_sim_exp/tags/Release_1.4
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4264d 05h	/mod_sim_exp/tags/Release_1.4
23	added descriptive comments	JonasDC	4264d 06h	/mod_sim_exp/tags/Release_1.4
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4267d 00h	/mod_sim_exp/tags/Release_1.4
21	changed x_i signal to xi	JonasDC	4268d 07h	/mod_sim_exp/tags/Release_1.4
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4268d 08h	/mod_sim_exp/tags/Release_1.4
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4273d 03h	/mod_sim_exp/tags/Release_1.4
18	updated stages with comments and renamed some signals for consistency	JonasDC	4274d 02h	/mod_sim_exp/tags/Release_1.4
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4274d 07h	/mod_sim_exp/tags/Release_1.4
16	package with modified generic parameter for register_n	JonasDC	4274d 20h	/mod_sim_exp/tags/Release_1.4

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[/] [mod_sim_exp/] [tags/] [Release_1.4] - Rev 35

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