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[/] [mod_sim_exp/] [tags/] [Release_1.4] - Rev 60

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Rev	Log message	Author	Age	Path
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4175d 05h	/mod_sim_exp/tags/Release_1.4
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4175d 05h	/mod_sim_exp/tags/Release_1.4
55	updated resource usage in comments	JonasDC	4179d 05h	/mod_sim_exp/tags/Release_1.4
54	generic fifo design: correctrly inferred by xilinx and altera	JonasDC	4179d 05h	/mod_sim_exp/tags/Release_1.4
53	correctly inferred ram for altera dual port ram	JonasDC	4179d 11h	/mod_sim_exp/tags/Release_1.4
52	correct inferring of blockram, no additional resources.	JonasDC	4179d 12h	/mod_sim_exp/tags/Release_1.4
51	true dual port ram for xilinx	JonasDC	4179d 13h	/mod_sim_exp/tags/Release_1.4
50	added folder for ram descriptions added experimental simple dual port ram implementation for xilinx	JonasDC	4179d 13h	/mod_sim_exp/tags/Release_1.4
47	added documentation for the IP core.	JonasDC	4259d 12h	/mod_sim_exp/tags/Release_1.4
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4259d 12h	/mod_sim_exp/tags/Release_1.4
45	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4259d 12h	/mod_sim_exp/tags/Release_1.4
44	toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface	JonasDC	4263d 06h	/mod_sim_exp/tags/Release_1.4
43	made the core parameters generics	JonasDC	4263d 06h	/mod_sim_exp/tags/Release_1.4
42	corrected wrong library name for mod_sim_exp_pkg	JonasDC	4269d 14h	/mod_sim_exp/tags/Release_1.4
41	removed deprecated files from version control	JonasDC	4269d 14h	/mod_sim_exp/tags/Release_1.4
40	adjusted core instantiation to new core module name	JonasDC	4277d 18h	/mod_sim_exp/tags/Release_1.4
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4278d 05h	/mod_sim_exp/tags/Release_1.4
38	deprecated design files because of new pipeline structure, will be removed shortly	JonasDC	4278d 11h	/mod_sim_exp/tags/Release_1.4
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4282d 08h	/mod_sim_exp/tags/Release_1.4
36	found bug in new pipeline structure, now working properly. (tested in sim) mod_sim_exp_core uses new flexible pipeline as default.	JonasDC	4283d 04h	/mod_sim_exp/tags/Release_1.4

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[/] [mod_sim_exp/] [tags/] [Release_1.4] - Rev 60

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