Rev |
Log message |
Author |
Age |
Path |
104 |
Release of version 1.5, this version supports an independent clock for the multiplier |
JonasDC |
3953d 19h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
101 |
added README file for simulation, minor update for Makefile clean target. |
JonasDC |
3953d 23h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
97 |
changes in makefile, and fifo's are now also in mod_sim_exp library |
JonasDC |
3988d 23h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
96 |
minor makefile update |
JonasDC |
3990d 00h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
94 |
BIG update: core now supports different clock speed for the multiplier core, so more performance is posible. currently this version is working in simulation and is being tested on hardware. Changes in this update include:
- changed RAM and memory to support different clocks
- new FIFO that supports dual clock (slightly modified version of generic_fifo's on OpenCores.org)
- parameter C_FIFO_DEPTH is now replace by C_FIFO_AW (address width of the fifo pointers)
- added logic for control signals to cross from one clock domain to another
- updated testbenches and interfaces accordingly
- added log of synthesis of the 2 new fifo's for Xilinx |
JonasDC |
4002d 20h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
90 |
reverted changes from previous revision, updated AXI version with testbench |
JonasDC |
4008d 19h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
84 |
AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS |
JonasDC |
4080d 03h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
70 |
updated testbench for use with new core parameters
updated makefile, added new sources |
JonasDC |
4121d 22h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
65 |
updated plb interface, now modulus is selectable and, fifo depth is adjustable.
updated makefile with new sources and update component in package |
JonasDC |
4129d 17h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
41 |
removed deprecated files from version control |
JonasDC |
4227d 01h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
31 |
put first cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4241d 03h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
30 |
put last cell logic of the pipeline in a separate design unit, tested and working |
JonasDC |
4241d 03h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
28 |
updated makefile for new pipeline sources |
JonasDC |
4241d 17h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
24 |
changed names of top-level module to mod_sim_exp_core |
JonasDC |
4245d 02h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |
3 |
updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation |
JonasDC |
4256d 18h |
/mod_sim_exp/tags/Release_1.5/sim/Makefile |