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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Rev 91

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Rev	Log message	Author	Age	Path
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4069d 14h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
76	testbench update	JonasDC	4106d 13h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4111d 09h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4206d 10h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
43	made the core parameters generics	JonasDC	4210d 04h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4229d 05h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4234d 13h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4246d 05h	/mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4250d 11h	/mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd

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