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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl/] [mod_sim_exp_core_tb.vhd] - Rev 93

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Rev	Log message	Author	Age	Path
84	AXI-Lite interface updated, now tested and verified on Xilinx FPGA renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS	JonasDC	4072d 18h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
76	testbench update	JonasDC	4109d 17h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4114d 13h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4209d 14h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
43	made the core parameters generics	JonasDC	4213d 07h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4232d 09h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4237d 17h	/mod_sim_exp/trunk/bench/vhdl/mod_sim_exp_core_tb.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4249d 09h	/mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4253d 15h	/mod_sim_exp/trunk/bench/vhdl/tb_multiplier_core.vhd

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