URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [bench/] [vhdl] - Rev 76

Rev	Log message	Author	Age	Path
76	testbench update	JonasDC	4108d 20h	/mod_sim_exp/trunk/bench/vhdl
70	updated testbench for use with new core parameters updated makefile, added new sources	JonasDC	4113d 16h	/mod_sim_exp/trunk/bench/vhdl
46	chance run_auto port or mod_sim_exp_core to exp_m	JonasDC	4208d 17h	/mod_sim_exp/trunk/bench/vhdl
43	made the core parameters generics	JonasDC	4212d 11h	/mod_sim_exp/trunk/bench/vhdl
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4231d 12h	/mod_sim_exp/trunk/bench/vhdl
26	testbench for only the montgommery multiplier	JonasDC	4233d 11h	/mod_sim_exp/trunk/bench/vhdl
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4236d 20h	/mod_sim_exp/trunk/bench/vhdl
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4248d 12h	/mod_sim_exp/trunk/bench/vhdl
2	First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules..	JonasDC	4252d 18h	/mod_sim_exp/trunk/bench/vhdl