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[/] [mod_sim_exp/] [trunk/] [bench] - Rev 90

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Rev Log message Author Age Path
90 reverted changes from previous revision, updated AXI version with testbench JonasDC 4001d 01h /mod_sim_exp/trunk/bench
84 AXI-Lite interface updated, now tested and verified on Xilinx FPGA
renamed C_DEVICE parameter, because of conflicts with restricted parameter in xilinx XPS		 JonasDC 4072d 09h /mod_sim_exp/trunk/bench
82 added first version of axi-lite interface and testbench for basic axi-lite operations, now under test JonasDC 4091d 06h /mod_sim_exp/trunk/bench
76 testbench update JonasDC 4109d 09h /mod_sim_exp/trunk/bench
70 updated testbench for use with new core parameters
updated makefile, added new sources		 JonasDC 4114d 04h /mod_sim_exp/trunk/bench
46 chance run_auto port or mod_sim_exp_core to exp_m JonasDC 4209d 06h /mod_sim_exp/trunk/bench
43 made the core parameters generics JonasDC 4212d 23h /mod_sim_exp/trunk/bench
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4232d 01h /mod_sim_exp/trunk/bench
26 testbench for only the montgommery multiplier JonasDC 4234d 00h /mod_sim_exp/trunk/bench
24 changed names of top-level module to mod_sim_exp_core JonasDC 4237d 09h /mod_sim_exp/trunk/bench
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4249d 01h /mod_sim_exp/trunk/bench
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4253d 06h /mod_sim_exp/trunk/bench

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