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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [core/] [mod_sim_exp_pkg.vhd] - Rev 42

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Rev	Log message	Author	Age	Path
41	removed deprecated files from version control	JonasDC	4220d 19h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
39	changed files to remove warnings from synthesis last cell logic is simplified because of redundant logic	JonasDC	4229d 10h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
37	changed names of some generics of the multiplier. moved the parameters for the core to the package of the core testbench now uses this parameters to adapt to different bit widths and new systolic pipeline now supports split or single pipeline	JonasDC	4233d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
34	operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below.	JonasDC	4234d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
31	put first cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4234d 22h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
30	put last cell logic of the pipeline in a separate design unit, tested and working	JonasDC	4234d 22h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4235d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4238d 21h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
23	added descriptive comments	JonasDC	4238d 22h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4241d 16h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
21	changed x_i signal to xi	JonasDC	4242d 23h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4243d 00h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4247d 19h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
18	updated stages with comments and renamed some signals for consistency	JonasDC	4248d 18h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4248d 23h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
16	package with modified generic parameter for register_n	JonasDC	4249d 12h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
9	added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code also renamed output s from n_adder to r, to keep same signal names	JonasDC	4249d 18h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd
3	updated vhdl sources with new header according to OC design rules and formated code added makefile and simulation input file for testbench simulation	JonasDC	4250d 13h	/mod_sim_exp/trunk/rtl/vhdl/core/mod_sim_exp_pkg.vhd

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