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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl] - Rev 22

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22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4230d 18h /mod_sim_exp/trunk/rtl/vhdl
21 changed x_i signal to xi JonasDC 4232d 02h /mod_sim_exp/trunk/rtl/vhdl
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4232d 02h /mod_sim_exp/trunk/rtl/vhdl
19 updated files with descriptive comments
changed signal names and removed redundant signals in stepping_logic		 JonasDC 4236d 21h /mod_sim_exp/trunk/rtl/vhdl
18 updated stages with comments and renamed some signals for consistency JonasDC 4237d 21h /mod_sim_exp/trunk/rtl/vhdl
17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4238d 02h /mod_sim_exp/trunk/rtl/vhdl
16 package with modified generic parameter for register_n JonasDC 4238d 15h /mod_sim_exp/trunk/rtl/vhdl
15 changed generic for register width from n to width for consistency JonasDC 4238d 15h /mod_sim_exp/trunk/rtl/vhdl
14 changed comments, file is now according to OC design rules JonasDC 4238d 15h /mod_sim_exp/trunk/rtl/vhdl
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules		 JonasDC 4238d 15h /mod_sim_exp/trunk/rtl/vhdl
12 updated comments, file is now completely according to design rules JonasDC 4238d 15h /mod_sim_exp/trunk/rtl/vhdl
10 changed signal input port names to correct name JonasDC 4238d 20h /mod_sim_exp/trunk/rtl/vhdl
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names		 JonasDC 4238d 20h /mod_sim_exp/trunk/rtl/vhdl
8 added descriptive comments JonasDC 4238d 23h /mod_sim_exp/trunk/rtl/vhdl
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4238d 23h /mod_sim_exp/trunk/rtl/vhdl
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4238d 23h /mod_sim_exp/trunk/rtl/vhdl
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4239d 01h /mod_sim_exp/trunk/rtl/vhdl
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4239d 15h /mod_sim_exp/trunk/rtl/vhdl
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4243d 21h /mod_sim_exp/trunk/rtl/vhdl

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