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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl] - Rev 44

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Rev Log message Author Age Path
44 toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface JonasDC 4219d 07h /mod_sim_exp/trunk/rtl/vhdl
43 made the core parameters generics JonasDC 4219d 07h /mod_sim_exp/trunk/rtl/vhdl
42 corrected wrong library name for mod_sim_exp_pkg JonasDC 4225d 15h /mod_sim_exp/trunk/rtl/vhdl
41 removed deprecated files from version control JonasDC 4225d 15h /mod_sim_exp/trunk/rtl/vhdl
40 adjusted core instantiation to new core module name JonasDC 4233d 19h /mod_sim_exp/trunk/rtl/vhdl
39 changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic		 JonasDC 4234d 07h /mod_sim_exp/trunk/rtl/vhdl
38 deprecated design files because of new pipeline structure, will be removed shortly JonasDC 4234d 12h /mod_sim_exp/trunk/rtl/vhdl
37 changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths

and new systolic pipeline now supports split or single pipeline		 JonasDC 4238d 09h /mod_sim_exp/trunk/rtl/vhdl
36 found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default.		 JonasDC 4239d 05h /mod_sim_exp/trunk/rtl/vhdl
34 operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. JonasDC 4239d 09h /mod_sim_exp/trunk/rtl/vhdl
33 default pipeline changed to old version, there seems to be an occasional error with new version. JonasDC 4239d 12h /mod_sim_exp/trunk/rtl/vhdl
32 new systolic pipeline structure now has split pipeline support, tested and verified in simulation. the core now uses this pipeline by default. JonasDC 4239d 13h /mod_sim_exp/trunk/rtl/vhdl
31 put first cell logic of the pipeline in a separate design unit, tested and working JonasDC 4239d 18h /mod_sim_exp/trunk/rtl/vhdl
30 put last cell logic of the pipeline in a separate design unit, tested and working JonasDC 4239d 18h /mod_sim_exp/trunk/rtl/vhdl
25 first version of new pipeline design. allows for more flexibility in nr of stages.
does not support split pipeline support yet. currently only works for single pipeline		 JonasDC 4240d 08h /mod_sim_exp/trunk/rtl/vhdl
24 changed names of top-level module to mod_sim_exp_core JonasDC 4243d 17h /mod_sim_exp/trunk/rtl/vhdl
23 added descriptive comments JonasDC 4243d 18h /mod_sim_exp/trunk/rtl/vhdl
22 updated the systolic pipeline with descriptive signal names and comments JonasDC 4246d 12h /mod_sim_exp/trunk/rtl/vhdl
21 changed x_i signal to xi JonasDC 4247d 20h /mod_sim_exp/trunk/rtl/vhdl
20 added comments, changed signal name of x_reg_i to x_reg.
File is now according to OC design rules		 JonasDC 4247d 20h /mod_sim_exp/trunk/rtl/vhdl

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