Rev |
Log message |
Author |
Age |
Path |
61 |
updated comments, added optional altera constraint |
JonasDC |
4129d 03h |
/mod_sim_exp/trunk/rtl/vhdl |
60 |
generic version of the fifo, not device specific anymore, uses dpram_generic
updated comments of RAM templates. |
JonasDC |
4131d 18h |
/mod_sim_exp/trunk/rtl/vhdl |
59 |
added templates that correctly infer RAM, for dual port en true dual port RAM
added general functions file, (used in the two RAM templates) |
JonasDC |
4131d 18h |
/mod_sim_exp/trunk/rtl/vhdl |
55 |
updated resource usage in comments |
JonasDC |
4135d 17h |
/mod_sim_exp/trunk/rtl/vhdl |
54 |
generic fifo design: correctrly inferred by xilinx and altera |
JonasDC |
4135d 18h |
/mod_sim_exp/trunk/rtl/vhdl |
53 |
correctly inferred ram for altera dual port ram |
JonasDC |
4136d 00h |
/mod_sim_exp/trunk/rtl/vhdl |
52 |
correct inferring of blockram, no additional resources. |
JonasDC |
4136d 01h |
/mod_sim_exp/trunk/rtl/vhdl |
51 |
true dual port ram for xilinx |
JonasDC |
4136d 01h |
/mod_sim_exp/trunk/rtl/vhdl |
50 |
added folder for ram descriptions
added experimental simple dual port ram implementation for xilinx |
JonasDC |
4136d 01h |
/mod_sim_exp/trunk/rtl/vhdl |
45 |
chance run_auto port or mod_sim_exp_core to exp_m |
JonasDC |
4216d 01h |
/mod_sim_exp/trunk/rtl/vhdl |
44 |
toplevel of the Modular Simultaneous Exponentiation IP core for the PLB interface |
JonasDC |
4219d 19h |
/mod_sim_exp/trunk/rtl/vhdl |
43 |
made the core parameters generics |
JonasDC |
4219d 19h |
/mod_sim_exp/trunk/rtl/vhdl |
42 |
corrected wrong library name for mod_sim_exp_pkg |
JonasDC |
4226d 03h |
/mod_sim_exp/trunk/rtl/vhdl |
41 |
removed deprecated files from version control |
JonasDC |
4226d 03h |
/mod_sim_exp/trunk/rtl/vhdl |
40 |
adjusted core instantiation to new core module name |
JonasDC |
4234d 07h |
/mod_sim_exp/trunk/rtl/vhdl |
39 |
changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic |
JonasDC |
4234d 18h |
/mod_sim_exp/trunk/rtl/vhdl |
38 |
deprecated design files because of new pipeline structure, will be removed shortly |
JonasDC |
4235d 00h |
/mod_sim_exp/trunk/rtl/vhdl |
37 |
changed names of some generics of the multiplier.
moved the parameters for the core to the package of the core
testbench now uses this parameters to adapt to different bit widths
and new systolic pipeline now supports split or single pipeline |
JonasDC |
4238d 21h |
/mod_sim_exp/trunk/rtl/vhdl |
36 |
found bug in new pipeline structure, now working properly. (tested in sim)
mod_sim_exp_core uses new flexible pipeline as default. |
JonasDC |
4239d 17h |
/mod_sim_exp/trunk/rtl/vhdl |
34 |
operand memory now supports custom operand widths, the internal memory stays the fixed 1536 bit, but the bus width is now adjustable to any size below. |
JonasDC |
4239d 20h |
/mod_sim_exp/trunk/rtl/vhdl |