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Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk] - Rev 17

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17 updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules JonasDC 4230d 07h /mod_sim_exp/trunk
16 package with modified generic parameter for register_n JonasDC 4230d 20h /mod_sim_exp/trunk
15 changed generic for register width from n to width for consistency JonasDC 4230d 20h /mod_sim_exp/trunk
14 changed comments, file is now according to OC design rules JonasDC 4230d 20h /mod_sim_exp/trunk
13 added some descriptive comments and added check for incorrect value's of width and block_width.
File is now according to OC design rules		 JonasDC 4230d 20h /mod_sim_exp/trunk
12 updated comments, file is now completely according to design rules JonasDC 4230d 20h /mod_sim_exp/trunk
11 simulation output folder JonasDC 4230d 23h /mod_sim_exp/trunk
10 changed signal input port names to correct name JonasDC 4231d 01h /mod_sim_exp/trunk
9 added descriptive comments, and renamed input mux_result from cell_1b_adder to b for a more generic multipurpose code
also renamed output s from n_adder to r, to keep same signal names		 JonasDC 4231d 01h /mod_sim_exp/trunk
8 added descriptive comments JonasDC 4231d 03h /mod_sim_exp/trunk
7 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4231d 04h /mod_sim_exp/trunk
6 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4231d 04h /mod_sim_exp/trunk
5 not needed on svn, is generated by testbench JonasDC 4231d 04h /mod_sim_exp/trunk
4 Modified the architecture, no longer uses Xilinx primitive, instead generic instantiation
added descriptive comments		 JonasDC 4231d 06h /mod_sim_exp/trunk
3 updated vhdl sources with new header according to OC design rules and formated code
added makefile and simulation input file for testbench simulation		 JonasDC 4231d 20h /mod_sim_exp/trunk
2 First version of VHDL source(working), still contains xilinx primitives and needs to be updated to the OpenCores design rules.. JonasDC 4236d 02h /mod_sim_exp/trunk
1 The project and the structure was created root 4238d 01h /mod_sim_exp/trunk

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