URL https://opencores.org/ocsvn/nextz80/nextz80/trunk

Subversion Repositories nextz80

[/] [nextz80] - Rev 18

Rev	Log message	Author	Age	Path
18	Fix Verilog module names	ndumitrache	1915d 18h	/nextz80
17	New INDEX instruction, extends memory addressing (see comments inside the Next8080CPU.v file).	ndumitrache	1945d 02h	/nextz80
16	I merged all the NextZ80 files, now there is a single Verilog file: NextZ80CPU.v I provided a stripped down version (Next8080CPU.v), compatible with 8080 (with some differences, see comments in the file header).	ndumitrache	1982d 22h	/nextz80
15		ndumitrache	1982d 22h	/nextz80
14		ndumitrache	1982d 22h	/nextz80
13	Instructions prefixed with DD/FD+CB don't activate M1 during opcode fetch (4th byte) - fixed.	ndumitrache	2110d 21h	/nextz80
12	Initialize a don't care bit, to prevent a wrong synthesis of the default value in some random cases.	ndumitrache	2459d 02h	/nextz80
11	Fix: clear I and R at reset Fix: prevent R set at INT in IM2 Simplify DAA module	ndumitrache	3775d 13h	/nextz80
10		ndumitrache	3779d 02h	/nextz80
9	fix some comments	ndumitrache	3781d 12h	/nextz80
8	make it more portable	ndumitrache	3781d 12h	/nextz80
7	Fix the bug related with Z flag and IN/OUT string instructions	ndumitrache	4471d 20h	/nextz80
6		ndumitrache	4806d 03h	/nextz80
5		ndumitrache	4826d 00h	/nextz80
4		ndumitrache	4827d 22h	/nextz80
3		ndumitrache	4831d 20h	/nextz80
2		ndumitrache	4831d 20h	/nextz80
1	The project and the structure was created	root	4831d 23h	/nextz80