| Rev |
Log message |
Author |
Age |
Path |
| 228 |
Added an initialization constant for the OPEN8_BUS_TYPE record. |
jshamlet |
1669d 20h |
/open8_urisc/trunk/VHDL |
| 227 |
Added a demonstration Open8_cfg.vhd file, which is used to configure the system constants. It also provides a function that makes it easy to merge read buses. |
jshamlet |
1670d 03h |
/open8_urisc/trunk/VHDL |
| 226 |
Forgot the updated package file... |
jshamlet |
1670d 07h |
/open8_urisc/trunk/VHDL |
| 225 |
Added Halt_Ack to go with Halt_Req. |
jshamlet |
1670d 07h |
/open8_urisc/trunk/VHDL |
| 224 |
Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. |
jshamlet |
1670d 09h |
/open8_urisc/trunk/VHDL |
| 223 |
Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. |
jshamlet |
1671d 02h |
/open8_urisc/trunk/VHDL |
| 222 |
Created a modified version of the epoch timer with a 32-bit, 1-uS resolution timer/comparator. |
jshamlet |
1671d 07h |
/open8_urisc/trunk/VHDL |
| 221 |
o8_vdsm8.vhd now has a default value assigned at compile time, o8_register.vhd was cleaned up some more. |
jshamlet |
1672d 02h |
/open8_urisc/trunk/VHDL |
| 220 |
More revision sections added |
jshamlet |
1672d 02h |
/open8_urisc/trunk/VHDL |
| 219 |
Added revision block and corrected creation date. |
jshamlet |
1672d 02h |
/open8_urisc/trunk/VHDL |
| 218 |
Revision sections added,
vdsm8.vhd added. |
jshamlet |
1672d 02h |
/open8_urisc/trunk/VHDL |
| 217 |
Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup. |
jshamlet |
1672d 03h |
/open8_urisc/trunk/VHDL |
| 216 |
Fixed missing parenthesis |
jshamlet |
1672d 05h |
/open8_urisc/trunk/VHDL |
| 215 |
More code cleanup |
jshamlet |
1672d 05h |
/open8_urisc/trunk/VHDL |
| 214 |
Initial add of some older code |
jshamlet |
1676d 03h |
/open8_urisc/trunk/VHDL |
| 213 |
Code and comment cleanup |
jshamlet |
1676d 04h |
/open8_urisc/trunk/VHDL |
| 212 |
Fixed issue with rewritten epoch timer not clearing alarm on set point write. |
jshamlet |
1676d 10h |
/open8_urisc/trunk/VHDL |
| 211 |
Ok, this time with feeling. Timer should now properly reset on interval update. |
jshamlet |
1677d 07h |
/open8_urisc/trunk/VHDL |
| 210 |
Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes. |
jshamlet |
1677d 10h |
/open8_urisc/trunk/VHDL |
| 209 |
Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core. |
jshamlet |
1677d 23h |
/open8_urisc/trunk/VHDL |
