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[/] [open8_urisc/] [trunk/] [VHDL/] [Open8_pkg.vhd] - Rev 183

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183 Renamed core to o8_cpu to match new naming scheme jshamlet 1550d 00h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
182 Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. jshamlet 1550d 00h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
181 Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. jshamlet 1550d 20h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
172 General code cleanup jshamlet 3074d 22h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
169 Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. jshamlet 3129d 23h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
153 Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.		 jshamlet 4732d 14h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
151 Fixed STO instruction and interrupt logic to avoid address bus corruption issues. jshamlet 4742d 17h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
10 corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values khays 4884d 01h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
8 Need to learn SVN... jshamlet 5212d 13h /open8_urisc/trunk/VHDL/Open8_pkg.vhd
7 Initial Upload jshamlet 5212d 13h /open8_urisc/trunk/open8_urisc/VHDL/Open8_pkg.vhd

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