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[/] [open8_urisc/] [trunk/] [VHDL/] [async_ser_tx.vhd] - Rev 209

Rev	Log message	Author	Age	Path
209	Fixed an issue in the PIT timer that caused an immediate interrupt on interval write, Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register, While cleaning elsewhere, founding a spacing issue in the CPU HDL, Added a 4k ROM and MW core.	jshamlet	1670d 16h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd
208	Removed unnecessary package references	jshamlet	1671d 01h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd
207	Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics.	jshamlet	1671d 18h	/open8_urisc/trunk/VHDL/async_ser_tx.vhd