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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_async_serial.vhd] - Rev 223

Rev	Log message	Author	Age	Path
223	Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up.	jshamlet	1543d 05h	/open8_urisc/trunk/VHDL/o8_async_serial.vhd
217	Broke out the vdsm8 as a separate entity, since it is used in several places, Even MORE code cleanup.	jshamlet	1544d 06h	/open8_urisc/trunk/VHDL/o8_async_serial.vhd
213	Code and comment cleanup	jshamlet	1548d 07h	/open8_urisc/trunk/VHDL/o8_async_serial.vhd
209	Fixed an issue in the PIT timer that caused an immediate interrupt on interval write, Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register, While cleaning elsewhere, founding a spacing issue in the CPU HDL, Added a 4k ROM and MW core.	jshamlet	1550d 02h	/open8_urisc/trunk/VHDL/o8_async_serial.vhd
207	Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics.	jshamlet	1551d 04h	/open8_urisc/trunk/VHDL/o8_async_serial.vhd