URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Rev 153

Rev	Log message	Author	Age	Path
153	Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded, Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.	jshamlet	4895d 15h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
151	Fixed STO instruction and interrupt logic to avoid address bus corruption issues.	jshamlet	4905d 18h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
10	corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values	khays	5047d 02h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
8	Need to learn SVN...	jshamlet	5375d 14h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
7	Initial Upload	jshamlet	5375d 14h	/open8_urisc/trunk/open8_urisc/VHDL/o8_cpu.vhd