URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_cpu.vhd] - Rev 156

Rev	Log message	Author	Age	Path
156	Optimized for timing, Flattened block structure to single entity.	jshamlet	4862d 23h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
155	Fixed additional interrupt logic bug, Optimized several blocks - including ALU, stack, program counter, and data path.	jshamlet	4863d 18h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
154	Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed.	jshamlet	4868d 21h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
153	Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded, Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered.	jshamlet	4895d 16h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
151	Fixed STO instruction and interrupt logic to avoid address bus corruption issues.	jshamlet	4905d 20h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
10	corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values	khays	5047d 04h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
8	Need to learn SVN...	jshamlet	5375d 16h	/open8_urisc/trunk/VHDL/o8_cpu.vhd
7	Initial Upload	jshamlet	5375d 16h	/open8_urisc/trunk/open8_urisc/VHDL/o8_cpu.vhd