Rev |
Log message |
Author |
Age |
Path |
187 |
Added the CPU_Halt input, only now as an input to the instruction decoder. The CPU_Halt line will assert the registered CPU_Halt_Req, which will cause the instruction decoder to abort the current instruction, reset the PC, then enter a hold state until the line is deasserted. Additionally, a very minor bug that could cause the SMSK instruction to effectively execute twice if interrupted was fixed. Lastly, cleaned up the comments even more. |
jshamlet |
1551d 09h |
/open8_urisc/trunk/VHDL/o8_cpu.vhd |
186 |
Merged the interrupt override logic into the case structure, simplifying how interrupts are processed. |
jshamlet |
1554d 09h |
/open8_urisc/trunk/VHDL/o8_cpu.vhd |
185 |
1) Fixed an apparently long-standing bug where the interrupt bit wasn't being cleared after an RTI
2) Modified the program counter logic to be simpler. It now always increments, and states control the increment using the offset field. A new set of constants was added to replace the old states.
3) Modified the ALU to always use Operand1 instead of ALU_Ctrl.Data (and removed the field in the record). A new ALU command, ALU_GMSK, was added, as it was the only instruction to set the .Data field to something other than Operand1 (Int_Mask)
4) Modified the package file so that flag names match what the assembler calls them. FL_Z is now PSR_Z, FL_GP1 is now PSR_GP4, etc.
5) Cleaned up the comments and code formatting |
jshamlet |
1554d 12h |
/open8_urisc/trunk/VHDL/o8_cpu.vhd |
183 |
Renamed core to o8_cpu to match new naming scheme |
jshamlet |
1556d 12h |
/open8_urisc/trunk/VHDL/o8_cpu.vhd |
182 |
Simplified the address generation logic at the expense of making LDX take one additional clock cycle. This allowed the address logic to be split out of the main state machine and simplified (greatly). During this process, a bug in SDO was found and fixed that caused it to return through the wrong pipe fill state wnen auto increment was disabled. |
jshamlet |
1556d 12h |
/open8_urisc/trunk/VHDL/Open8.vhd |
181 |
Altered the RSP instruction to allow the stack pointed to either be restored from registers or stored to registers based on the status of a processor bit. Also modified LDX to simplify the address logic. |
jshamlet |
1557d 08h |
/open8_urisc/trunk/VHDL/Open8.vhd |
172 |
General code cleanup |
jshamlet |
3081d 10h |
/open8_urisc/trunk/VHDL/Open8.vhd |
169 |
Corrected issue with CMP and SBC generating an inverted carry flag and added new constants to the package file to simplify interfacing new modules. |
jshamlet |
3136d 11h |
/open8_urisc/trunk/VHDL/Open8.vhd |
168 |
Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component, |
jshamlet |
3915d 07h |
/open8_urisc/trunk/VHDL/Open8.vhd |
167 |
Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus. |
jshamlet |
3923d 05h |
/open8_urisc/trunk/VHDL/Open8.vhd |
164 |
Modified the data path to allow the bus to go idle while waiting for an interrupt. This makes it easier to debug code that uses the WAI instruction, as both Wr_Enable and Rd_Enable go low. |
jshamlet |
4559d 01h |
/open8_urisc/trunk/VHDL/Open8.vhd |
162 |
Added optional generic to specify that the BRK instruction implements a WAit_for_Interrupt (WAI) instruction instead. Logically emulates INT, but without triggering a soft interrupt. Note that the NOP instruction maps to BRK, and will not function correctly if this option is set. |
jshamlet |
4649d 18h |
/open8_urisc/trunk/VHDL/Open8.vhd |
156 |
Optimized for timing,
Flattened block structure to single entity. |
jshamlet |
4706d 09h |
/open8_urisc/trunk/VHDL/Open8.vhd |
155 |
Fixed additional interrupt logic bug,
Optimized several blocks - including ALU, stack, program counter, and data path. |
jshamlet |
4707d 03h |
/open8_urisc/trunk/VHDL/Open8.vhd |
154 |
Fixed problem with missing data path override in interrupt logic. Should resolve issues with processor crashing when an interrupt occurs as a STO instruction is being executed. |
jshamlet |
4712d 06h |
/open8_urisc/trunk/VHDL/Open8.vhd |
153 |
Fixed bug in interrupt logic that caused stack pointer to increment if interrupt occurred as specific instructions were being decoded,
Fixed bug in interrupt logic where instruction caching would remain enabled during an interrupt, causing improper execution depending on what instruction was in the decode stage as the interrupt is trigered. |
jshamlet |
4739d 02h |
/open8_urisc/trunk/VHDL/Open8.vhd |
151 |
Fixed STO instruction and interrupt logic to avoid address bus corruption issues. |
jshamlet |
4749d 05h |
/open8_urisc/trunk/VHDL/Open8.vhd |
10 |
corrected implementation for BTT to match V8/ARClite definition, changed sense of reset, corrected comments to match source values |
khays |
4890d 14h |
/open8_urisc/trunk/VHDL/Open8.vhd |
8 |
Need to learn SVN... |
jshamlet |
5219d 01h |
/open8_urisc/trunk/VHDL/Open8.vhd |
7 |
Initial Upload |
jshamlet |
5219d 01h |
/open8_urisc/trunk/open8_urisc/VHDL/Open8.vhd |