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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_ram_1k.vhd] - Rev 242

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242 Added write protect logic to the RAM cores and system timer as part of scheme to keep tasks from messing up the scheduler or other task's memory. The RAM is now divided into regions with a separate write mask register. The write mask register itself is only writeable with the I bit is set (during an interrupt or by setting it using STP PSR_I). The 1K memory is divided into 16, 64 byte regions while the 4K memory is divided into 32, 128 byte regions. The system timer simply checks for the I bit being set when the write protect generic is set.

Note that setting the write_protect generic false, or leaving it unset, will keep the previous behavior.		 jshamlet 1494d 08h /open8_urisc/trunk/VHDL/o8_ram_1k.vhd
224 Finished new Open8 bus record, which now includes the clock, reset and a microsecond tick. The CPU now accepts a clock and pll_locked signal, which it uses to generate the system reset in the bus record. It also contains a simple microsecond counter to feed the usec_tick in the record. This logic was removed from the real time clock and system timer entities, which now use the global version. Bus connections should be dramatically simplified, as only the read logic and interrupts are still run as separate signals. jshamlet 1521d 11h /open8_urisc/trunk/VHDL/o8_ram_1k.vhd
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1522d 04h /open8_urisc/trunk/VHDL/o8_ram_1k.vhd
217 Broke out the vdsm8 as a separate entity, since it is used in several places,
Even MORE code cleanup.		 jshamlet 1523d 05h /open8_urisc/trunk/VHDL/o8_ram_1k.vhd
194 Cleaned up licensing sections jshamlet 1537d 07h /open8_urisc/trunk/VHDL/o8_ram_1k.vhd
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1537d 08h /open8_urisc/trunk/VHDL/o8_ram_1k.vhd
174 Added ROM/RAM wrappers jshamlet 3082d 05h /open8_urisc/trunk/VHDL/o8_ram_1k.vhd

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