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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Rev 177

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Rev Log message Author Age Path
177 Fixed comments in RTC module jshamlet 2892d 15h /open8_urisc/trunk/VHDL/o8_rtc.vhd
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.
jshamlet 2897d 12h /open8_urisc/trunk/VHDL/o8_rtc.vhd
172 General code cleanup jshamlet 3092d 12h /open8_urisc/trunk/VHDL/o8_rtc.vhd
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,
jshamlet 3926d 09h /open8_urisc/trunk/VHDL/o8_rtc.vhd
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.
jshamlet 3934d 07h /open8_urisc/trunk/VHDL/o8_rtc.vhd

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