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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_rtc.vhd] - Rev 209

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209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1523d 12h /open8_urisc/trunk/VHDL/o8_rtc.vhd
194 Cleaned up licensing sections jshamlet 1531d 18h /open8_urisc/trunk/VHDL/o8_rtc.vhd
191 Cleaned up comments, added back the OPEN8_NULLBUS constant, and added some new modules for ADCs and LCD displays.
Also made the button input module more configurable by moving the debounce code to a separate entity and using generics to instantiate it.		 jshamlet 1531d 19h /open8_urisc/trunk/VHDL/o8_rtc.vhd
190 Fixed a bug in CPU where RTI/RTS wasn't idling the instruction cache, causing intermittent failures where RTI would execute as RTS, corrupting the stack;
Fixed a bug in the real-time clock where the uSec tick generator would stop if the PIT timer value was left/set to 0x00.		 jshamlet 1543d 16h /open8_urisc/trunk/VHDL/o8_rtc.vhd
189 Merged changes from private repository,
added ceil_log2 function to Open8_pkg, since it is used to calculate RAM vectors,
cleaned up comments and removed local copies of the ceil_log2 function from peripherals.		 jshamlet 1544d 17h /open8_urisc/trunk/VHDL/o8_rtc.vhd
177 Fixed comments in RTC module jshamlet 2876d 19h /open8_urisc/trunk/VHDL/o8_rtc.vhd
176 Fixed documentation errors,
Modified uSec_Tick such that it is always generated regardless of the interval.		 jshamlet 2881d 17h /open8_urisc/trunk/VHDL/o8_rtc.vhd
172 General code cleanup jshamlet 3076d 16h /open8_urisc/trunk/VHDL/o8_rtc.vhd
168 Simplified write data path logic,
Converted RTC to packed BCD,
Corrected several bugs in real time clock component,		 jshamlet 3910d 13h /open8_urisc/trunk/VHDL/o8_rtc.vhd
167 Updated CPU model; Pipelined ALU control signals to improve fMAX, corrected issue with interrupt controller priority not being obeyed, fixed bug in auto-indexing instructions where the upper register wasn't being properly incremented, cleaned up code to make the processor model easier to follow.
Added several useful modules that use the Open8 bus.		 jshamlet 3918d 12h /open8_urisc/trunk/VHDL/o8_rtc.vhd

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