URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Rev 198

Rev	Log message	Author	Age	Path
198	Removed debugging memory	jshamlet	1546d 16h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
196	Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored)	jshamlet	1546d 17h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
192	Added SDLC packet engine	jshamlet	1547d 12h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd