URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Rev 201

Rev	Log message	Author	Age	Path
201	Fixed comments regarding RX Checksum location	jshamlet	1648d 20h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
200	Renamed dual-port buffer to match other entities.	jshamlet	1648d 20h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
199	Added monitor ram for debugging and fixed issue with dual-port read path.	jshamlet	1648d 20h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
198	Removed debugging memory	jshamlet	1649d 04h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
196	Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored)	jshamlet	1649d 05h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
192	Added SDLC packet engine	jshamlet	1650d 01h	/open8_urisc/trunk/VHDL/o8_sdlc_if.vhd