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[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Rev 202

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Rev Log message Author Age Path
202 Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.
jshamlet 1544d 10h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
201 Fixed comments regarding RX Checksum location jshamlet 1546d 07h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
200 Renamed dual-port buffer to match other entities. jshamlet 1546d 07h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1546d 07h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
198 Removed debugging memory jshamlet 1546d 15h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
196 Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) jshamlet 1546d 16h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
192 Added SDLC packet engine jshamlet 1547d 12h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd

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