OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] [VHDL/] [o8_sdlc_if.vhd] - Rev 223

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
223 Added an OPEN8_BUS_TYPE record to simplify connection to Open8 modules. The CPU now passes and Open8_Bus out, which supplies the bus address, write enable, write data, and read enable. Read data and interrupts are still handled as separate signals, since they are muxed/connected at the next level up. jshamlet 1543d 05h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
206 Merged interrupt logic with other clocked process. jshamlet 1554d 22h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
205 More code and comment cleanup for the new SDLC engine jshamlet 1554d 22h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
204 Fixed more incorrect comments jshamlet 1554d 23h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
202 Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.		 jshamlet 1555d 06h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
201 Fixed comments regarding RX Checksum location jshamlet 1557d 03h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
200 Renamed dual-port buffer to match other entities. jshamlet 1557d 03h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1557d 03h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
198 Removed debugging memory jshamlet 1557d 11h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
196 Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) jshamlet 1557d 12h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd
192 Added SDLC packet engine jshamlet 1558d 08h /open8_urisc/trunk/VHDL/o8_sdlc_if.vhd

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.