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[/] [open8_urisc/] [trunk/] [VHDL] - Rev 276

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276 More comment fixes jshamlet 1472d 07h /open8_urisc/trunk/VHDL
275 Fixed a minor comment error. jshamlet 1474d 01h /open8_urisc/trunk/VHDL
274 Updated comments with more corrections jshamlet 1474d 08h /open8_urisc/trunk/VHDL
273 Updated comments with corrections jshamlet 1474d 10h /open8_urisc/trunk/VHDL
271 Removed deleted generic define. jshamlet 1484d 10h /open8_urisc/trunk/VHDL
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.		 jshamlet 1484d 10h /open8_urisc/trunk/VHDL
269 Modified the write data path to use separate enumerated states rather than reuse the .reg field to improve performance. jshamlet 1486d 23h /open8_urisc/trunk/VHDL
268 Added a 16-input external interrupt manager and dedicated SPI tx-only transmitter (for use with DACs, etc.). Also updated the soft-DACs with cleaned up HDL. jshamlet 1487d 00h /open8_urisc/trunk/VHDL
267 Corrected the file description to indicate this is an example package. jshamlet 1487d 00h /open8_urisc/trunk/VHDL
266 Accidentally uploaded incorrect example file for Open8_cfg.vhd jshamlet 1487d 00h /open8_urisc/trunk/VHDL
265 Fixed a bug where "reg" wasn't being initialized with Poly_Init at reset. jshamlet 1579d 09h /open8_urisc/trunk/VHDL
264 Updated comments jshamlet 1589d 06h /open8_urisc/trunk/VHDL
263 Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

Also separated the SDLC TX and RX interrupts so that they could be handled separately.		 jshamlet 1589d 06h /open8_urisc/trunk/VHDL
262 Added comments to LCD controllers - specifically that reading either register 0 or 1 will return the ready status. This code was already present, but not mentioned in the register map. jshamlet 1598d 10h /open8_urisc/trunk/VHDL
261 Increased delay timer to 7 bits for button press detection. jshamlet 1605d 10h /open8_urisc/trunk/VHDL
260 Added missing comments for Sequential_Interrupts generic, as well as comments explaining portions of the CPU operations. jshamlet 1618d 09h /open8_urisc/trunk/VHDL
259 Fixed issue where Write_Fault wasn't defaulting to '0' when Write_Protect was set to FALSE,
Added a pulse interval measurement entity,
Fixed comments.		 jshamlet 1618d 10h /open8_urisc/trunk/VHDL
258 Fixed write bug in o8_ltc2355_2p.vhd, added a newer Open8_cfg.vhd, and the sys_tick.vhd utility entity. jshamlet 1619d 08h /open8_urisc/trunk/VHDL
257 Fixed misnamed signal in o8_7seg.vhd and added a replacement switch interface that handles both static and pushbutton switches. jshamlet 1619d 09h /open8_urisc/trunk/VHDL
256 Removed unused generic from the status_led.vhd and cleaned up comments on the CPU jshamlet 1619d 10h /open8_urisc/trunk/VHDL

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