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[/] [open8_urisc/] [trunk/] [VHDL] - Rev 292

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Rev Log message Author Age Path
292 Updated the o8_trig_delay entity by:
1) Added a global interrupt enable,
2) Added the ability to trigger on both the pre- and post-arm trigger input
3) Added the ability to read the external input on offset 7		 jshamlet 1249d 12h /open8_urisc/trunk/VHDL
290 Added an additional generic "Rotation_Ignores_Carry" that removes the carry logic from the ROL/ROR instructions such that they now rotate 'normally',
Added an alias for PSR_GP4 named PSR_S, as it is now used to switch the function of the RSP instruction. The internal opcode hasn't changed, but it allows assembly code to use PSR_S or BRS/BNS when performing RSP related operations.		 jshamlet 1292d 02h /open8_urisc/trunk/VHDL
289 Added back the delay for the cursor home command, since it is slow on most Hitachi compatible LCD panels. jshamlet 1309d 13h /open8_urisc/trunk/VHDL
288 Removed hard-wired R/Wn output and replaced it with a note that the R/Wn line must be tied low either in firmware or on the board. jshamlet 1310d 09h /open8_urisc/trunk/VHDL
287 Fixed mangled comments and revisioning dates. jshamlet 1311d 08h /open8_urisc/trunk/VHDL
286 Added initial cut of a "universal" character LCD driver. Allows for adjustment of address setup, enable high, and cycle times. Also has built-in timers for handling timing on certain commands. jshamlet 1311d 09h /open8_urisc/trunk/VHDL
285 Added checksum byte to vector tx/rx to avoid issues with serial line noise glitching the receiver. Also modified the transmitted to take any generic argument, rather than canned arguments. jshamlet 1318d 12h /open8_urisc/trunk/VHDL
284 Corrected the vhdl unit name and description for o8_7seg.vhd jshamlet 1431d 23h /open8_urisc/trunk/VHDL
283 Altered SDLC bitclock check on TX to NOT block when tested by software, but to instead ignore packet write requests if BClk_Okay is low. This allows software to continue checking BClk_Okay in a polling loop. jshamlet 1435d 10h /open8_urisc/trunk/VHDL
282 Modified the SDLC core transmit states to have consistent naming. jshamlet 1435d 11h /open8_urisc/trunk/VHDL
281 Added pre-initialization to the dual-port RAM signals. jshamlet 1435d 14h /open8_urisc/trunk/VHDL
280 Got rid of silly aliases that connected the dual-port memory and the arbitration logic. jshamlet 1435d 14h /open8_urisc/trunk/VHDL
279 More comment cleanup jshamlet 1436d 11h /open8_urisc/trunk/VHDL
278 Flattened the SDLC interface to fewer files and eliminated the package file. jshamlet 1437d 05h /open8_urisc/trunk/VHDL
276 More comment fixes jshamlet 1472d 08h /open8_urisc/trunk/VHDL
275 Fixed a minor comment error. jshamlet 1474d 02h /open8_urisc/trunk/VHDL
274 Updated comments with more corrections jshamlet 1474d 09h /open8_urisc/trunk/VHDL
273 Updated comments with corrections jshamlet 1474d 10h /open8_urisc/trunk/VHDL
271 Removed deleted generic define. jshamlet 1484d 10h /open8_urisc/trunk/VHDL
270 Moved CPU internal constants to o8_cpu.vhd and replace the generic that set the RSP direction flag with a constant instead. This removes the need to expose internal architectural flags externally.

Also added a hard-coded version register that takes a major and minor value as bytes using generics. This is a read-only register to the CPU.		 jshamlet 1484d 10h /open8_urisc/trunk/VHDL

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