OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk] - Rev 213

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
213 Code and comment cleanup jshamlet 1588d 12h /open8_urisc/trunk
212 Fixed issue with rewritten epoch timer not clearing alarm on set point write. jshamlet 1588d 18h /open8_urisc/trunk
211 Ok, this time with feeling. Timer should now properly reset on interval update. jshamlet 1589d 15h /open8_urisc/trunk
210 Modified the timers to reset on new interval write. This avoids an issue in the original design where the timer had to reach zero before updating, potentially causing unwanted interrupts.
Also added a flag to the CPU to allow interrupts to be processed sequentially based on the state of the I bit. This one is set to false by default, as it is a significant change in interrupt behavior. Long, and reentrant, ISRs can clear the I bit prematurely to allow themselves to be interrupted.
Lastly, added the I bit to the exported flags for possible use in memory protection schemes.		 jshamlet 1589d 18h /open8_urisc/trunk
209 Fixed an issue in the PIT timer that caused an immediate interrupt on interval write,
Fixed an issue in the epoch timer that resulted in a spurious interrupt due to extra LSB's being set by default in the set point register,
While cleaning elsewhere, founding a spacing issue in the CPU HDL,
Added a 4k ROM and MW core.		 jshamlet 1590d 06h /open8_urisc/trunk
208 Removed unnecessary package references jshamlet 1590d 16h /open8_urisc/trunk
207 Added a simple 8-bit, fixed asynchronous serial interface with compile time settable bit-rate, parity enable, and parity mode generics. jshamlet 1591d 09h /open8_urisc/trunk
206 Merged interrupt logic with other clocked process. jshamlet 1595d 04h /open8_urisc/trunk
205 More code and comment cleanup for the new SDLC engine jshamlet 1595d 04h /open8_urisc/trunk
204 Fixed more incorrect comments jshamlet 1595d 04h /open8_urisc/trunk
203 Removed an extra delay FF from the bitclock rising edge signal for the clock slave configuration to better center the rising edge pulse on the receive signal. jshamlet 1595d 11h /open8_urisc/trunk
202 Fixed receiver bug that caused false flag detection,
Split the large sdlc_serial_ctrl entity into sub-entities to make debugging easier.		 jshamlet 1595d 11h /open8_urisc/trunk
201 Fixed comments regarding RX Checksum location jshamlet 1597d 09h /open8_urisc/trunk
200 Renamed dual-port buffer to match other entities. jshamlet 1597d 09h /open8_urisc/trunk
199 Added monitor ram for debugging and fixed issue with dual-port read path. jshamlet 1597d 09h /open8_urisc/trunk
198 Removed debugging memory jshamlet 1597d 17h /open8_urisc/trunk
197 Fixed incorrect comments jshamlet 1597d 17h /open8_urisc/trunk
196 Modified the update logic to allow direct writes to offset 0xFE for refreshing the clock status. This way, any write to the clock status register will immediately be undone. (Writing 0x00 to offset 0xFF is once-more ignored) jshamlet 1597d 18h /open8_urisc/trunk
195 Added dual-port RAM core for SDLC interface. jshamlet 1598d 12h /open8_urisc/trunk
194 Cleaned up licensing sections jshamlet 1598d 12h /open8_urisc/trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.