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[/] [open_hitter/] [trunk/] [bench/] [vhdl] - Rev 22

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Rev Log message Author Age Path
22 mixed rising_edge / falling_edge logic removed stvhawes 3421d 12h /open_hitter/trunk/bench/vhdl
21 flakey sim bugs (1/10 test 2 fails) stvhawes 3421d 15h /open_hitter/trunk/bench/vhdl
20 search_control_sim prepped stvhawes 3428d 10h /open_hitter/trunk/bench/vhdl
19 search_control is up for simulation (ghdl) - tidied extra testbenches stvhawes 3435d 09h /open_hitter/trunk/bench/vhdl
18 search_control is up for simulation (ghdl) stvhawes 3435d 09h /open_hitter/trunk/bench/vhdl
17 persistent bug: search_control_wrapper.vhd:230:21:@36us:(assertion error): search_control_wrapper: test: 3 bad id stvhawes 3440d 20h /open_hitter/trunk/bench/vhdl
16 minor fixes to search_control test bench stvhawes 3447d 06h /open_hitter/trunk/bench/vhdl
15 adding in search_control and testbench stvhawes 3448d 11h /open_hitter/trunk/bench/vhdl
14 search_item_wrapper bench debugged stvhawes 3454d 07h /open_hitter/trunk/bench/vhdl
13 test bench for search_item stvhawes 3457d 12h /open_hitter/trunk/bench/vhdl
12 wrapper test for search_item stvhawes 3462d 21h /open_hitter/trunk/bench/vhdl
10 split source files to sime and rtl stvhawes 3477d 13h /open_hitter/trunk/bench/vhdl
8 sim sequence error fixed, so 20% success -> 100% success for unit test on fpga stvhawes 3478d 12h /open_hitter/trunk/bench/vhdl
7 split clock/byte_ready and fix logic stvhawes 3483d 05h /open_hitter/trunk/bench/vhdl
6 fixing synthesizable stvhawes 3484d 14h /open_hitter/trunk/bench/vhdl
5 fixing synthesizable stvhawes 3484d 18h /open_hitter/trunk/bench/vhdl
3 developing ideas around unit test / fpga verification stvhawes 3485d 06h /open_hitter/trunk/bench/vhdl
2 initial sources, wrappers for regression test harness stvhawes 3496d 09h /open_hitter/trunk/bench/vhdl

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