URL https://opencores.org/ocsvn/openarty/openarty/trunk

Subversion Repositories openarty

[/] [openarty/] [trunk/] [rtl/] [cpu] - Rev 50

Rev	Log message	Author	Age	Path
50	Updated the CPU and distribution in general to handle 8-bit bytes.	dgisselq	2662d 14h	/openarty/trunk/rtl/cpu
49	Moved the location of the ZIPSYSTEM in memory, made the artyboard.h constants more friendly and more complete, fixed two bugs in the CPU (jumps to breaks, and s/w clearing of icache), added a NO_USERMODE option to the CPU, and more. Rebuild any user programs before using this build.	dgisselq	2787d 03h	/openarty/trunk/rtl/cpu
43	Cleaned up the CPU memory documentation.	dgisselq	2807d 07h	/openarty/trunk/rtl/cpu
42	Fixed up the CPU so that it passes a multiply test bench, in addition to the CPU test.	dgisselq	2807d 07h	/openarty/trunk/rtl/cpu
36	Lots of changes, see the git changelog for details.	dgisselq	2813d 17h	/openarty/trunk/rtl/cpu
32	Brought the CPU to its first working version, to include demo.	dgisselq	2823d 15h	/openarty/trunk/rtl/cpu
30	Network transmit and MIG memory both work now, though the clock speed has been dropped to 80.125MHz.	dgisselq	2824d 08h	/openarty/trunk/rtl/cpu
25	The memory now works. However, the core speed has been lowered to 81.25MHz to do this. The top level file is no longer fasttop.v, but toplevel.v.	dgisselq	2860d 13h	/openarty/trunk/rtl/cpu
3	Initial set of files. The flash appears to work, memory hasn't been started, the MDIO controller works in simulation, etc. Everything below fasttop.v works at 200MHz (not the CPU---yet).	dgisselq	2907d 15h	/openarty/trunk/rtl/cpu