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[/] [openarty/] [trunk/] [sw/] [host] - Rev 51

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51 Updated host software, following 8-bit byte updates. dgisselq 2626d 16h /openarty/trunk/sw/host
49 Moved the location of the ZIPSYSTEM in memory, made the artyboard.h constants
more friendly and more complete, fixed two bugs in the CPU (jumps to breaks,
and s/w clearing of icache), added a NO_USERMODE option to the CPU, and more.
Rebuild any user programs before using this build.		 dgisselq 2751d 05h /openarty/trunk/sw/host
38 ZipLoad can now load programs to non-reset locations. dgisselq 2771d 09h /openarty/trunk/sw/host
37 Updated documentation and copyright. dgisselq 2771d 09h /openarty/trunk/sw/host
36 Lots of changes, see the git changelog for details. dgisselq 2777d 19h /openarty/trunk/sw/host
34 These updates bring the distribution along to the point where both the GPS
clock subsecond tracking, as well as the OLEDrgb controller now work.		 dgisselq 2781d 08h /openarty/trunk/sw/host
33 Fixed the network receive CRC and MAC checking, and added ip-checking and
minimum packet length checking to the receiver.		 dgisselq 2786d 14h /openarty/trunk/sw/host
32 Brought the CPU to its first working version, to include demo. dgisselq 2787d 17h /openarty/trunk/sw/host
31 Initial network is now working. Adding CPU control files to repository. dgisselq 2788d 09h /openarty/trunk/sw/host
30 Network transmit and MIG memory both work now, though the clock speed has
been dropped to 80.125MHz.		 dgisselq 2788d 09h /openarty/trunk/sw/host
22 A useful script for programming the device, given that the current device
program includes a valid comms interface.		 dgisselq 2853d 10h /openarty/trunk/sw/host
18 The device can now program and configure itself, allowing bootstrap possibilities.
`		 dgisselq 2853d 10h /openarty/trunk/sw/host
16 This returns the scope to its original configuration, where the decode()
function is not allowed to have any side effects.		 dgisselq 2855d 10h /openarty/trunk/sw/host
14 All changes made as a part of getting the flash driver up and running. Today,
it successfully programmed a configuration into the Arty via wbprogram, so ...
that's been my last/best test.		 dgisselq 2855d 10h /openarty/trunk/sw/host
6 Minor updates, mostly to support the development of the DDR3 SDRAM--such
as creating addresses for the debugging scope used to figure out what's
going on with it.		 dgisselq 2856d 13h /openarty/trunk/sw/host
4 Initial host software pack. dgisselq 2871d 17h /openarty/trunk/sw/host

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