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[/] [openmsp430/] [trunk/] [core/] - Rev 162

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154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4378d 20h /openmsp430/trunk/core
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4463d 19h /openmsp430/trunk/core
149 Update simulation regression result parser.
Fixed failing SFR test (due to newer MSPGCC version).
Implement request http://opencores.org/bug,view,2171 (burst accesses through the serial debug interface)		 olivier.girard 4466d 21h /openmsp430/trunk/core
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4516d 20h /openmsp430/trunk/core
142 Beautify the linker script examples. olivier.girard 4537d 21h /openmsp430/trunk/core
141 Update verification environment to support MSPGCC Uniarch (based on GCC 4.5 and later) olivier.girard 4541d 20h /openmsp430/trunk/core
139 Add some SVN ignore patterns olivier.girard 4554d 06h /openmsp430/trunk/core
138 Update simulation scripts to support Cygwin out of the box for Windows users. olivier.girard 4554d 06h /openmsp430/trunk/core
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4585d 21h /openmsp430/trunk/core
132 Update FPGA examples with the POP.B bug fix olivier.girard 4598d 20h /openmsp430/trunk/core
130 Fixed POP.B bug (see Bugtracker http://opencores.org/bug,assign,2137 ) olivier.girard 4606d 19h /openmsp430/trunk/core
128 Fixed CALL x(SR) bug (see Bugtracker http://opencores.org/bug,view,2111 ) olivier.girard 4682d 20h /openmsp430/trunk/core
122 Add coverage report generation (NCVERILOG only)
Add support for the ISIM Xilinx simulator.		 olivier.girard 4754d 21h /openmsp430/trunk/core
117 To facilitate commercial adoption of the openMSP430, the core has moved to a modified BSD license. olivier.girard 4858d 22h /openmsp430/trunk/core
115 Add linker script example. olivier.girard 4883d 21h /openmsp430/trunk/core
112 Modified comment. olivier.girard 4891d 20h /openmsp430/trunk/core
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4892d 20h /openmsp430/trunk/core
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4948d 19h /openmsp430/trunk/core
105 Removed dummy memory read access for the MOV/PUSH/CALL/RETI instructions.
These were not problematic but this is simply cleaner that way.		 olivier.girard 4963d 20h /openmsp430/trunk/core
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 4969d 02h /openmsp430/trunk/core

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