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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] [ram.v] - Rev 186

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103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.
olivier.girard 4896d 07h /openmsp430/trunk/core/bench/verilog/ram.v
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.
olivier.girard 4937d 02h /openmsp430/trunk/core/bench/verilog/ram.v
72 Expand configurability options of the program and data memory sizes. olivier.girard 5112d 03h /openmsp430/trunk/core/bench/verilog/ram.v
23 Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).
olivier.girard 5448d 06h /openmsp430/trunk/core/bench/verilog/ram.v
17 Updated header with SVN info olivier.girard 5474d 01h /openmsp430/trunk/core/bench/verilog/ram.v
2 Upload complete openMSP430 project to the SVN repository olivier.girard 5509d 01h /openmsp430/trunk/core/bench/verilog/ram.v

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