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[/] [openmsp430/] [trunk/] [core/] [bench] - Rev 205

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205 Thanks again to Johan W. good feedback, the following updates are implemented:
- Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
- Update oscillators enable generation to relax a critical timing paths in the ASIC version.
- Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).		 olivier.girard 3414d 06h /openmsp430/trunk/core/bench
202 Add DMA interface support + LINT cleanup olivier.girard 3428d 06h /openmsp430/trunk/core/bench
200 Major verificaiton and benchmark update to support both MSPGCC and RedHat/TI GCC toolchains. olivier.girard 3589d 05h /openmsp430/trunk/core/bench
192 Number of supported IRQs is now configurable to 14 (default), 30 or 62. olivier.girard 3989d 07h /openmsp430/trunk/core/bench
154 The serial debug interface now supports the I2C protocol (in addition to the UART) olivier.girard 4417d 06h /openmsp430/trunk/core/bench
151 Add possibility to configure custom Program, Data and Peripheral memory sizes. olivier.girard 4502d 04h /openmsp430/trunk/core/bench
145 Add Dhrystone and CoreMark benchmarks to the simulation environment. olivier.girard 4555d 06h /openmsp430/trunk/core/bench
134 Add full ASIC support (low-power modes, DFT, ...).
Improved serial debug interface reliability.		 olivier.girard 4624d 06h /openmsp430/trunk/core/bench
111 Re-organized the "openMSP430_defines.v" file.
Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.		 olivier.girard 4931d 06h /openmsp430/trunk/core/bench
106 Separated the Timer A defines from the openMSP430 ones.
Added the "dbg_en" port in order to allow a separate reset of the debug interface.
Added the "core_en" port (when cleared, the CPU will stop execution, the dbg_freeze signal will be set and the aclk & smclk will be stopped).
Renamed "per_wen" to "per_we" to prevent confusion with active low signals.
Removed to missing unused flops when the DBG_EN is not defined (thanks to Mihai contribution).		 olivier.girard 4987d 05h /openmsp430/trunk/core/bench
103 Removed the timescale from all RTL files.
Added possibility to exclude the "includes" statements from the RTL.		 olivier.girard 5007d 12h /openmsp430/trunk/core/bench
99 Small fix for CVER simulator support. olivier.girard 5012d 06h /openmsp430/trunk/core/bench
98 Added support for VCS verilog simulator.
VPD and TRN waveforms can now be generated.		 olivier.girard 5012d 06h /openmsp430/trunk/core/bench
94 Thanks to Mihai-Costin Manolescu's contribution, the simulation scripts now support the following simulators:
- Icarus Verilog
- Cver
- Verilog-XL
- NCVerilog
- Modelsim		 olivier.girard 5016d 06h /openmsp430/trunk/core/bench
84 Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.		 olivier.girard 5048d 07h /openmsp430/trunk/core/bench
76 Add possibility to simulate C code within the "core" environment. olivier.girard 5114d 06h /openmsp430/trunk/core/bench
72 Expand configurability options of the program and data memory sizes. olivier.girard 5223d 08h /openmsp430/trunk/core/bench
67 Added 16x16 Hardware Multiplier. olivier.girard 5370d 15h /openmsp430/trunk/core/bench
65 Add possibility to disable waveform dumping by setting the OMSP_NODUMP environment variable to 1. olivier.girard 5381d 05h /openmsp430/trunk/core/bench
54 Update FPGA projects with the combinatorial loop fixed. olivier.girard 5409d 08h /openmsp430/trunk/core/bench

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